In memory design, sending bit cell information to the outside world (i.e., external to an integrated circuit) requires fast level conversion of small analog signals, namely the complementary bit lines to full rail signals. In the prior art this conversion was accomplished by using a sense amplifier which converted the complementary bit lines to full rail signals, on complementary global data lines, and drove them to a latch which held the data value until the next memory access cycle. However, in many memory implementations the metal lines used to implement the complementary global data lines were shared by a significant number of memory blocks. Thus these complementary global data lines were heavily loaded due to the junction capacitance from the unselected dynamic sense amplifiers within the unselected memory blocks as well as the length of these global data lines. As a consequence the complementary global data lines had slow propagation delay and long rise and fall times. As a result the read access time for prior art memories was negatively impacted (i.e., increased) due to the behavior of the complementary global data lines. Also, the constant full range charging of these highly capacitive global data lines has had a significant impact on power consumption.